1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device that is intended to form a contact plug in an interlayer insulating film.
2. Background Art
For example, flash memory devices, such as NAND flash memories, can retain data even after the power supply is turned off. Therefore, the flash memory devices are widely used as multimedia cards.
Some of the flash memory devices have a matrix array of stacked gate electrodes formed on a semiconductor substrate with a gate insulating film interposed therebetween and thus contain a large number of memory cells and select gate transistors. These flash memory devices are increased in integration density in this way.
In general, flash memory devices have gate electrodes (a floating gate electrode and a control gate electrode) and a gate insulating film interposed therebetween that are formed on a semiconductor substrate.
Recently, there is a remarkable demand for increased write and erase speed of the memory cells. To increase the write and erase speed of the memory cells, the resistance of the control gate electrode has to be reduced. To achieve the reduction of the resistance of the control gate electrode, according to a method proposed, an alloy of a metal having a low resistance, such as cobalt, is used for the alloy layer formed on the control gate electrode.
In formation of the alloy layer, it is difficult to use a high-temperature thermal processing or the like. Therefore, a film of a metal having low resistance is formed on the base layer of the control gate electrode, and the base layer is divided before alloying. Then, in the period between the division and the alloying, an insulating film is formed between memory cells and between select gate transistors.
However, in some case, the insulating film is formed stepwise by stacking an oxide film as a side wall spacer and a nitride film as an etching stopper for forming a contact plug.
In this case, as the insulating film becomes thicker, an adequate space cannot be ensured between gate electrodes (in particular, between select gate transistors), which are required to be downsized. Thus, it is difficult to form a contact plug (a contact plug for a bit line, for example) having an adequate diameter between the select gate transistors.
In addition, the recent trend of downsizing has led to higher aspect ratio, and formation of the contact hole has become more difficult, so that the occurrence rate of insufficient contact holes has increased. In addition, although the half pitch of the cell array and the space between select gate transistors have to be reduced in order to reduce the chip area to achieve downsizing, the latter task is difficult because of the problem of contact plug formation described above.
In particular, the degree of downsizing of the contact hole depends on the exposure and resolution capability and the contact forming technique. Therefore, in the present circumstances, the limit of the exposure and resolution capability is equivalent to the limit of downsizing of contacts.
According to a conventional method of manufacturing a semiconductor device, an interlayer insulating film is etched using a first conductive film as a mask to form a contact hole, a second conductive film is formed to fill the contact hole, and the second conductive film is partially removed by chemical mechanical polishing (CMP) to form a connection pad (see Japanese Patent Laid-Open No. 11-330238, for example).
According to the conventional method of manufacturing a semiconductor device, etching of the contact plug due to misalignment is prevented in a lithography step, thereby preventing increase of the contact resistance.
However, even the conventional method of manufacturing a semiconductor device cannot form a contact plug that is smaller than the limit of the exposure and resolution capability of the contact hole.